Bachelor’s degree in Electrical/Electronics Engineering or equivalent practical experience.
5 years of experience with ASIC design implementation and convergence.
Experience with scripting (e.g., writing production scripts for implementation tools).
Experience with CAD flow development.
Experience delivering Power Performance Area goals across projects.
Understanding Static Timing Analysis and sign-off convergence methodology.
Ability to evaluate multiple vendor solutions and drive tool decisions.
Knowledge of technology node across foundries and industry standard implementation tools.
Ability to work with external vendors and drive design improvements.
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
In this role, you will be responsible for developing block constraints and synth flow for SoC’s. You will work with designers to understand their needs and building efficient solutions that scale across multiple projects and nodes.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Develops block implementation flow capable and manage gate designs.
Work with design teams to understand requirements and enable scalable solutions.
Work across functional domains to enable faster sign off convergence during Place and Route.
Explore Power Performance Area improvements to deliver customized solutions for IP’s.
Drive electronic design automation (EDA) vendors to improve their tools to deliver custom solutions for Google.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy (https://careers.google.com/eeo/) and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) .