Qualcomm India Private Limited
Engineering Group, Engineering Group > Hardware Engineering
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
Multiple positions for 3-10 years of experience in design verification of complex Qualcomm propriety DSP IP
DSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm’s multi-tier SoC roadmap targeted for mobile space
Qualcomm is the largest fabless design company in the world, generating over $15 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software and related services to nearly every mobile device maker and operator in the global wireless marketplace
Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams
Implement and improve System Verilog Testbench Architecture
Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency
Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals
Hand-on simulations and debug
Complete all required verification activities at IP level and insure high quality commercial success of our products
Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis
Responsible gate level simulation bring up, gate level verification with timing simulations
Responsible for power aware RTL and gate level simulation
3-10 years’ experience in processor/ASIC design verification
Solid background and understanding of Digital Design, Processor Architecture and Processor Verification
Expertise in System Verilog Testbench Architecture and implementation
Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence
Scripting/Automation Skills — Perl, Python, Shell, Make file TCI
Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts
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